Wafer Level Packaging:-

Wafer Level Packaging is in high demand for a variety of reasons, including the need to reduce package size and height, streamline the supply chain, and reduce overall costs, but also for performance reasons. It is a process of packaging the silicon chips either it is part of a silicon wafer or separation of the dies from the silicon wafer after the dicing process and then packaging them.

This process delivers greater bandwidth, speed, reliability, uses less power, and offers a wider range of form factors for multi-chip packages used in mobile consumer electronics, high-end supercomputing, artificial intelligence, and IoT devices. It consists of enhancing the wafer fabrication methods to include device connectivity and protection. Although WLP is now a widely recognized package choice, its initial popularity was limited by concerns about the SMT assembly process. Since the package’s introduction, assembly skills and methodologies have improved; still, silicon damage remains an issue. After dicing the wafer, the side or top of the die remains exposed, and the silicon remains sensitive to chipping, cracking, and other handling damage during the assembly process. Nowadays, the cost of Wafer Level Packaging is determined from the wafer or packaging procedure. If large-scale manufacturing is necessary, the amount of labor must be raised and the production cost will rise as a result.

The semiconductor industry’s approach to wafer-level manufacturing, known as the Flex-Line technique, frees customers from wafer diameter limits while providing supply chain optimization and considerable cost savings not feasible with a traditional manufacturing flow. This technique production technology represents a substantial paradigm change from conventional wafer level manufacturing, providing unrivaled flexibility and cost reductions for both Fan-In and Fan-Out Wafer Level Packaging. This technique essentially eliminates wafer dimension limits while allowing for supply chain simplicity and considerable cost savings not attainable with conventional methods.

There are two categories of Wafer Level Packaging technologies:-

Fan-In Wafer Level Packaging:-

The devices that are finally packed are of the same size as the die itself is known as Fan-in WLP. The process is similar to bumping processes for Flip-Chip packages and may be thought of as an extension of front-end manufacturing in that it involves the whole wafer. This packaging has better electrical and thermal performance. There are various types of Fan-in WLP technologies developed to improve solder ball reliability such as Bump on Nitride, Bump on Polymer, and Copper Post WLP. It consists of solder bump and under bump metallurgy seated on the thin in-organic passivation as shown below.

In this structure with UBM, the UBM functions only as an adhesive layer that facilitates the electroplating process. To avoid a direct connection with the silicon base, the solder ball rests on the polymer layer.

In the below structure, the thick copper pillars are electroplated by using epoxy encapsulation. The solder ball sits on the Copper Post.

Fan-in WLP continues to expand, drawing new automotive and industrial applications. Currently available capacity requires complete and extra volume. In today’s world, technical advancement is focused on expanding die sizes and decreasing pitch. The semiconductor industry is entering a new era in which device scaling and price reduction will not follow the same path as in previous decades. Advanced nodes no longer generate the needed cost profit, and R&D costs for fresh new lithography solutions have increased. New market developments are likely soon, with IoT poised to dethrone mobile as the market leader. All Redistribution Layers are routed towards the die’s center in the Fan-in WLP structure as shown below in the image.

Fan-Out Wafer Level Packaging:-

In this process, the individual dies are packaged once the wafer is diced. The package size is frequently larger than the die size. Rather than placing the dies on the substrate, the Fan-out Packages use an epoxy mold compound to embed them and then form the solder balls on top of the die. Fan-out began as a packaging innovation designed to increase the I/O footprint of wafer-level chip-scale packages while shielding the four sides from crack damage. The main benefit of both fan-out wafer-level and panel-level packaging is cost reduction, mostly due to lower labor costs, while material costs per device are comparable to traditional packaging.

There are several advantages of Fan-out WLP which are given below:-

• Reduced Package Thickness
• It has a capability for the increased number of I/O.
• High thermal performance
• Improved electrical performance

This packaging structure is similar to the Ball Grid Array Packages. For Fan-out WLP, moisture sensitivity becomes a major concern. Encapsulated moisture is a specific and distinct type of loading that interacts with the mechanical behaviors of mold compounds. One of the problems in Fan-out WLP is to create materials that do not delaminate when exposed to moisture loading.

When ambient moisture is absorbed by mold compounds and other polymer materials, it condenses in free-volumes in polymer materials and along with interfaces. During the reflow process, which takes only a few minutes, the collected moisture will evaporate and generate a high internal vapor pressure. During reflow, the temperature reaches a high of 220 to 250 degrees. When temperatures rise over their glass transition temperatures, the plastic materials become highly pliable.  The movement of the IC within the reconstituted wafer is one of the challenges of fan-out packaging. This misplacement might result in a lack of connectivity with the bond pad in typical fan-out packaging methods where masks are used, clearly resulting in a defective unit.

In the Fan-out WLP, the Redistribution Layers are routed towards the inside and outside of the die as shown below.

5D and 3D Packaging:-

2.5D and 3D technologies are becoming more important in the industry. This technology has successfully delivered pioneering solutions that helped bring advanced ASIC products to the marketplace. The multiple silicon chips that are arranged inside the same package are referred to as the 2.5D Packaging. This methodology has been used in those robust applications where high-speed performance and low power are crucial. The 2.5D architecture has a lot of challenges to do with memory units. The memories are very costly and many users have spent a significant amount of time in this region. The first solution was to do it one step at a time. In other words, before putting the memory on the silicon interposer, include an ASIC.

In 2.5D architecture, the chips are not piled on each other but the chips are on silicon or organic interposer. This packaging requires less energy to drive various types of signals due to shorter distances between the multiple chips which are arranged in a planer. This architecture refers to a die stacking package that uses interposers to get the best internet connectivity performance. The interposer’s tiny die is the most difficult challenge in 2.5D packaging. Everything tested in the 2.5D architecture is downsized. Manufacturing interposers necessitate changes to both processes and materials. Large, high-aspect-ratio TSV are included. The key to 2.5D is the use of an interposer structure, commonly a silicon interposer with TSV. It is not possible to test the electrical connectivity between the wafer’s top and bottom sides in 2.5D. It is much easier to probe the wafer’s backside, which can only be done after the back-grinding process.

3D Packaging is an Advanced Packaging Technology in which more than two layers of electronics components are piled together and electrically interconnected with each other. A Through-Silicon Via (TSV) is the high-performance vertical interconnect access technique that passes through a wafer or silicon die as shown below in the images. TSV is used for creating 3D Integrated Circuits or 3D packages. The fine pitch capability gap between the assembly substrate and the integrated circuit board can be bridged using the Si interposer with TSV (Through Silicon Via). It can assist in maintaining the pad pitch scaling route without being constrained by the assembly substrate technology. While the semiconductor industry has experienced a paradigm shift from 2.5D to 3D Packaging, implementation will be slow and careful.  The most difficult packaging reliability issue at the time comes from chip-packaging interaction caused by thermal stress produced breaking of the ultra-low dielectric layer in the multi-layered interconnect structure, and TSV can function as an interposer to reduce the problem.

Die stacking is used in 3D packaging, which is a newer packaging technology. It is established to fulfill the demands of higher-density semiconductor memory chips used in microprocessors. It builds on the 2.5 D packaging material’s technologies, which have generated enormous capacity and performance improvements over earlier 2D designs.

Beyond Moore’s Law, 3D integration promises to expand integration density even further, with the potential to massively reduce interconnect delays and improve system performance. It also provides a versatile technique to carry out the Heterogeneous System-on-chip architecture by integrating disparate technologies such as flash memories, logics, radio-frequency, and optoelectronic devices. This packaging technology is used in various applications such as,

• In high-level Graphics Processing Unit
• In Programmable Gate Array Integrated Circuits
• Long-range network servers

System-In-Package:-

The System-In-Package module market has risen dramatically in recent years and it is now one of the fastest-growing packaging technologies in the semiconductor industry due to its lower cost, smaller form factor, higher levels of integration, and improved electrical performance. This module is mostly adopted by users for wireless communication applications including the RF sections of cellular phones and wireless connectivity. SIPs are not the same as Chiplets, however, there is some overlap. Both techniques address the increasing difficulty and cost of developing SoCs. The vast majority of modules used in high-volume SiP production are double-sided, but the next generation of applications, particularly mobile phones, will use either four-layer or high-density connectivity. These modules can handle compact form factor needs, although at a much higher cost than previous generations. Industries must address the known-good-die (KGD) issue while creating a SiP package. The final product yield is determined by multiplying all component yields together, making a single die failure extremely expensive. Because devices couldn’t be properly validated until the final assembly was accomplished, early multichip modules were very expensive. Failures were frequently not detected until it was too late, requiring the removal of modules with a single faulty component.

Nowadays SiP offering solves the KGD problem by using smaller dice with higher yields. Furthermore, modern SiP devices contain less onboard memory that requires burn-in and use dice with proven functionality, similar to a discrete component. The progress of very high wafer probe yields–in the high range–through optimal process centering and highly sophisticated diagnostic procedures have reduced KGD fallout to a noise level for SiP viability. However, the effort is still being done to replace failing memory dice in terms of speed, bits, and addresses. It is the new advanced integration technology in which the number of Integrated Circuits such as processor, logic gates, and flash memory is enclosed together in the same housing is referred to as the System-In-Package. It is a combination of active electrical components with various functionalities and other passive components. It is typically used in multiple applications like CPU, Flash memories, DRAM, and Digital Logics. This technology accepts various types of modules and bare chips for assembly and arrangement.

The die-attach procedure is one of the most difficult issues in SiP assembly, especially in RF design. GaAs dice as thin as 75 microns or fewer are used in current technologies, and they get incredibly hot due to the amount of power they carry; also, they are sensitive to wire bond lengths and surrounding circuitry. The SiP manufacturing method is put to the test when it comes to products with compact form factors, such as cell phones. System-In-Package has been around in the form of multi-chip modules since the 1980s. Instead of putting chips on a printed circuit board, they can be combined into a single package to save cost or shorten the distances over which electrical signals have to travel. This technology is enabling functionality and providing opportunity across various electronics applications, with features that deliver high-performance and cost-effectiveness.

This packaging requires distinct integration of single or multiple chips such as a high-level processor, DRAM, flash memory, surface mount device (SMD) MEMS device, sensors, and other active/passive components. The main advantages of SIP are given below:-

• Size reduction
• Complexity reduction
• Design effort reduction
• Power Reduction
• Cost-efficient

In the below image, the SiP shows a microprocessor, SRAM, and flash memory chips packaged together in the same housing.

Bumping and Flip-Chip:-

In this process, the chip is not wire bonded for interconnection but is flipped face to face with the substrate surface. The interconnection between the silicon chip and the substrate is made through the array of bumps that are placed on the bonded pads of the die surface. Solder bumps have been used to attach the silicon die to the packaging substrate in Flip-Chip Packages for about 35 years. The use of copper pillars as part of the interconnections between the die and the substrate (leadframe) is relatively new. In a conventional solder bump design, solder forms the whole electrical and mechanical connection between the die and the package. The interconnection takes on an almost spherical shape when the solder melts during the reflow process, but the exact dimensions, both diameter, and height. Copper pillar technology allows making a cylindrical junction between the bottom of the die and the top of the package substrate with additional control over the diameter and standoff height.

Switching to a copper pillar flip chip helped Intel to escape the industry-wide problem of lowTg underfill because the company kept its copper pillar design with high-Tg underfill. Flip-Chip Packages are used in ASICs and microprocessor applications where high performance and speed are required. It provides a solution for high electrical performance due to the shorter electrical path between the die and the substrate. It means devices can pass their signal at high speed while dissipating heat. The array of bumps under the die allows the die to small in size which makes it cost-effective.

While copper pillar technology has several advantages, constructing dependable joints involves balancing several factors, many of which have opposing impacts. To avoid six primary difficulties, a balance of design elements affecting the die, interconnection, underfill, substrate, and lid must be achieved.

• Cracking of the low-k dielectric during the Die Attach or underfill.
• War-page, which can affect package co-planarity and the thickness of the thermal interface material bond line.
• Field reliability of Flip-Chip interconnections especially solders fatigue during thermal cycling.
• Stress on the backside of the die during the Die Attach, which could cause the die to fracture.
• Thermal fatigue resistance of second-level solders joints.
• Failure of electro-migration.

The Flip-Chip Packaging allows making voltage and grounding connections to the internal points of the chip which results in its better performance. Flip-Chip Packaging benefits include high signal density, better power dissipation, better ground and power connectivity, and low signal inductance. Open fails have been usually at the center at the die bump area and can be divided into two types:

• The bumps are lifted off the substrate pad.
• A trace that connects to the substrate pad immediately breaks.

A solution to the problem of die-bump lifting is as follows:

• Increase the machine’s built-in points of the alignment evaluation system. This will fine-tune the die level to get it as close to the genuine parallel surface about the substrate as possible.
• In addition, in front of the following process stage, infrared reflow, a smart camera is attached. Depending on how thoroughly the die surface is adjusted, this can lead the aligned bumped die to be rejected before the reflow process, and the die to be re-aligned.

Chip Scale Packages:-

In the 1990s, the concept of chip-size packaging evolved. Wafer-level CSPs emerged as cost-effective options for a wide range of applications, from low-pin-count devices like EEPROMs to ASICs and microprocessors. Chip Scale Packages are mostly used in compact and portable electronic systems which are higher in demand. Chip-Scale Package is a type of surface-mountable device with an area of fewer than 1.2 times the original die area.

Due to small interconnections between the die and the substrate, electrical performance is enhanced. The main advantage of Chip Scale Packages over Ball Grid Array Packaging is that they conserve a significant amount of space. This packaging technology has many advantages especially in its electrical testing, epoxy attachment, handling, and soldering. The advantages of Chip Scale Packages include the smallest size, lower weight, easier assembly process, lower costs, and improvement in electrical performance.

The first image is showing the electrical interconnection between the die and the leadframe of the SMD device.

In the second image, the bonding zone of the SMD device is covered by an epoxy molding compound.

Redistribution Layer:-

The Redistribution process is defined as the addition of other sets of extra metal and dielectric layers on a wafer surface. Every Integrated circuit has a set of input and output pads after it is manufactured. Those pads are wire-bonded with the pins of the substrate. It is used in Fan-in WLP, Fan-out WLP, 2.5D, and 3D packaging. The Integrated fan-out wafer-level chip-scale package is introduced for modern system-in-package designs with larger Input/Output counts and higher interconnection density. The industry is now producing various types of fan-out packages with varying specs and flows. The line and space features in the redistribution layers are one common specification.

The Redistribution Layer is formed of one or more layers formed on a die. The width of the metal traces and the space between them are referred to as line and space. A redistribution layer in an integrated fan-out package is an extra metal layer for inter-chip connections. The Redistribution Layer routing problem for fan-out packages has become a critical problem for modern electronic system architectures to provide flexible and compact inter-chip connections. In advanced high-density integrated fan-out packages, multiple RDLs with flexible vias are often adopted. To merge chips from several technological nodes into a single package, unconventional pad structures must be considered.

A Redistribution Layer on a chip is an extra layer of metal as shown in the image below. This layer allows to bond out from different spots on the chip, making Chip-to-Chip bonding easier. These Redistribution Layers require metallization and thin-film polymer to re-route the pads to desired locations.

Embedded Die Substrate:-

A single die or multiple dies are embedded within the core of an organic laminated substrate is referred to as the Embedded Die Substrate Packaging. Copper-plated vias are used to connect the components. Embedded Die Packaging is different than other types of packaging. In IC packages, the devices are mounted on top of a substrate and the substrate serves as an interface between the devices and a board in a system. Then, the die is electrically interconnected to other electronics components on the substrate.

Due to its lower thermal and electrical resistivity, it improves the power performance of the device. It has shorter interconnections which minimize power loss and distortion. This packaging provides various options such as tiny packages, electronics modules, and system-in-boards for various applications.

The advantages of Embedded Die Packaging are listed below:-

• The Embebbed chip enables more space for other passive components.
• The overall design flexibility is now shifted from 2.5D to 3D.

There are several difficulties with embedded die packing as well. There are some manufacturing issues because it combines modern packaging and PCB processes. Furthermore, the ecosystem is still in its immaturity. Embedded die costs are still too high, and yield is often too low. The embedded die packaging market is still a limited sector, with a forecast increase from $15 million in 2017 to $18 million in 2018. The market is estimated to reach more than $50 million by 2023. Embedded die packaging is not new, but it has been restricted to niche applications due to a variety of problems. Nonetheless, the technology seems promising. Furthermore, embedded die packaging offers numerous alternatives for varied applications, such as micro packages, modules, and system-in-boards.

MEMS and Micro-System Packaging:-

The packaging provides support and protection to delicate core elements e.g. silicon chips from mechanical or environmentally induced damages e.g. heat and humidity. The effect of packaging parameters on dependability is referred to as MEMS packaging. The issue of material properties is one of the key scientific challenges of MEMS. The qualities of the materials are determined by how they are used and processed, as well as the thermal treatments to which they are subjected and even the exact pieces of equipment employed during manufacturing. Materials are utilized in small quantities, and suppliers are hesitant to sell small quantities or develop new products for niche markets.

MEMS devices are often manufactured at the microscopic level. A typical device level process flow before packaging includes wafer surface micromachining or bulk micromachining, generation of the desired pattern, various bonding techniques, and subsequent interconnection. A bulk of a wafer is wet or dry etched to build micromachined structures in silicon crystal or deposited or grown layers on silicon in bulk micromachining. Bonding is another important method used during fabrication that includes field assisted thermal bonding, thermal fusion bonding, eutectic bonding. The reliability of a surface micromachined device is determined by the materials used and the processes used to build it up using thin-film processing, among other factors. In general, high residual stresses are created in thin films, which affect device performance to varying degrees. Bulk micromachined devices have their own set of challenges with reliability. Sharp corners from anisotropic etching, adhesion issues as previously described, and overall poor quality due to a nonoptimized process including several manufacturing stages are examples of these.

If micromachined structures and electronics are to be merged on a single chip, the compatibility of the two processes, such as micromachining and electronics, must be considered. These concerns differ significantly between the two technologies. The clean room is frequently a compatibility issue for bulk micromachining using anisotropic etchants. When KOH is utilized, contamination of the wafer surface limits the amount of further processing that can be done. The major considerations for surface micromachining are frequently the additional thermal budgets of depositions, annealing, and masking during etching. When silicon dioxide is employed as the sacrificial layer, the etchant is typically HF-based. This causes issues for the aluminum used in metallization.

This packaging can be differentiated into metal or ceramic and Plastic Packaging.

Plastic Packaging is very cost-efficient for packaging MEMS devices. These fragile devices must be protected before packaging processes. Plastic Packaging of MEMS is accomplished by the wafer-level capping process. Throughout the Packaging process, the device is protected by the plastic cap.

Ceramic/metal Packaging consists of a base and a lid. The dies are attached to the base surface during the Die Attach process and the metal pads on the die and the base surface are electrically interconnected by the Wire Bond process. Then the package is capped and sealed. This technique is used for TO-3, TO-18, and TO-66 types of metal-can packages.